When processing semiconductor wafers, different process steps have been found to result in changes to the flatness, bow or warpage across the area of the wafer (referred to herein collectively as global wafer “curvature”). These changes in wafer curvature can directly impact photolithographic alignment and focus. When the global wafer curvature changes enough from one stage of the process flow to another, such as between the gate pattern to contact pattern, photolithographic alignment can become difficult, or even not possible (e.g., due too large a differential in the depth of focus within a scanner/stepper shot), and a significant yield loss may result.
Known approaches for controlling global wafer curvature generally involve changing the process(es) that are found to generate the most curvature. For example, in a MOS process flow, the source/drain anneal temperature or time at the peak temperature may be reduced to reduce the magnitude of the curvature induced. However, since the functions of the source/drain anneal functions include dopant activation, such changes can result in degraded device performance, such as an increase in on resistance (RON). For example, RON is an important performance figure of merit for MOSFET switching devices and is defined as the ohmic resistance that exists between an input and an output pin of a MOSFET switch when the switch is closed and passing a signal. A lower RON*Area allows a designer to use a smaller MOSFET to meet ON resistance requirements for a given application, which reduces the area and cost of a power integrated circuit.